Generally, a flash memory device includes a source connection layer that connects the sources of unit cells to form a source line. As a conventional method for forming the source connection layer, a metal contact method includes forming a contact in the sources of unit cell(s) and connecting the contacts. However, this method is inappropriate for highly integrated devices because a contact margin needs to be provided. To implement the high-integration of a device, recently, a source line of an impurity diffusion layer has been employed. The source line of an impurity diffusion layer is formed by means of a self-aligned source (SAS) process.
For example, Korean Publication Patent No. 2003-49450 discloses a method for smoothly applying a cell source ion implantation process by compensating damage of a photoresist pattern for the formation of a source line using a SAS etching process. Korean Publication Patent No. 2001-104910 provides a method for preventing the substrate silicon of active regions from being damaged by etching a field oxide layer after the formation of a polysilicon layer for a floating gate.
As other examples, U.S. Pat. No. 5,955,759 to Ismail et al. discloses a method for making a field effect transistor. The method by the Ismail et al. patent comprises forming raised source/drain contacts self-aligned to preexisting junction regions and then forming the gate dielectric and a self-aligned metal or metal/polysilicon gate which may be T-shaped in order to reduce the parasitic gate resistance. U.S. Pat. No. 5,552,331 to Hsu et al. discloses a method for forming spacers with different width along with a gate to protect gate-edges and adjacent source regions during an etching process for the formation of a self-aligned source.
FIGS. 1a through 1c illustrate, in cross-sectional views, the process of forming a source line of a flash memory device according to a conventional method.
Referring to FIG. 1a, a device isolation layer (not shown) is formed on a semiconductor substrate 11. The device isolation layer defines a field region and an active region. A tunnel oxide layer 12 is formed in the active region of the substrate 11. A stack gate structure is formed on the tunnel oxide layer 12. The stack gate structure comprises a floating gate 13, a dielectric layer 14, and a control gate 15. To reduce word line resistance according to high-integration of device, the control gate 15 generally has a multi-layer structure comprising a polysilicon and a metal material selected from a group consisting of WSix, W, CoSix, TiSix, etc. Next, a photoresist pattern 16 is formed over the stack gate structure. The photoresist pattern is formed by means of a SAS mask process and defines a source line region.
Referring to FIG. 1b, a device isolation layer (not shown) in the source line region is removed by means of a SAS etching process. As a result, the semiconductor substrate 11 in the source line region is completely exposed. After the completion of the SAS etching process, a baking process is performed. Through the SAS etching and the baking processes, the photoresist pattern 16 becomes thin and hardened.
Referring to FIG. 1c, a cell source ion implantation process is performed using the thin and hardened photoresist pattern 17 as a mask. As a result, a source line 18 in which impurity ions are implanted is formed in the source line region of the semiconductor substrate 11.
However, such conventional technology may cause defects in silicon lattices due to the etching and the ion implantation for the formation of source and drain and, therefore, the thickness of the oxide layer on either side of the gate may not become uniform.